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<title>One-instruction set computer</title>

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One-instruction set computer

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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="1-bit_computing" title="1-bit computing">1-bit computing</a>.</div>

A one-instruction set computer (OISC), sometimes referred to as an ultimate <a href="RISC" class="mw-redirect" title="RISC">reduced instruction set computer</a> (URISC), is an <a href="Abstract_machine" title="Abstract machine">abstract machine</a> that uses only one instruction – obviating the need for a <a href="Machine_language" class="mw-redirect" title="Machine language">machine language</a> <a href="Opcode" title="Opcode">opcode</a>.<a href="#cite_note-urisc-1">[1]</a><a href="#cite_note-caamp-2">[2]</a><a href="#cite_note-agut-3">[3]</a> With a judicious choice for the single instruction and given arbitrarily many resources, an OISC is capable of being a <a href="Universal_computer" class="mw-redirect" title="Universal computer">universal computer</a> in the same manner as traditional computers that have multiple instructions.<a href="#cite_note-caamp-2">[2]</a>: 55 OISCs have been recommended as aids in teaching computer architecture<a href="#cite_note-urisc-1">[1]</a>: 327 <a href="#cite_note-caamp-2">[2]</a>: 2 and have been used as computational models in structural computing research.<a href="#cite_note-agut-3">[3]</a> The first <a href="Carbon_nanotube_computer" title="Carbon nanotube computer">carbon nanotube computer</a> is a <a href="1-bit_computing" title="1-bit computing">1-bit</a> one-instruction set computer (and has only 178 transistors).<a href="#cite_note-4">[4]</a>

<div class="mw-heading mw-heading2"><h2 id="Machine_architecture">Machine architecture</h2></div>

In a <a href="Turing_completeness" title="Turing completeness">Turing-complete model</a>, each memory location can store an arbitrary integer, and – depending on the mode, there may be arbitrarily many locations. The instructions themselves reside in memory as a sequence of such integers.

There exists a class of <a href="Universal_computer" class="mw-redirect" title="Universal computer">universal computers</a> with a single instruction based on bit manipulation such as bit copying or <a href="Bit_inversion" title="Bit inversion">bit inversion</a>. Since their memory model is finite, as is the memory structure used in real computers, those bit manipulation machines are equivalent to real computers rather than to Turing machines.<a href="#cite_note-mazonka-5">[5]</a>

Currently known OISCs can be roughly separated into three broad categories:

<ul><li>Bit-manipulating machines</li>

<li>Transport triggered architecture machines</li>

<li>Arithmetic-based Turing-complete machines</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Bit-manipulating_machines">Bit-manipulating machines</h3></div>

<a href="Bit_manipulation" title="Bit manipulation">Bit-manipulating</a> machines are the simplest class.

<div class="mw-heading mw-heading4"><h4 id="FlipJump">FlipJump</h4></div>

The <a rel="nofollow" class="external text" href="https://esolangs.org/wiki/FlipJump">FlipJump</a> machine has 1 instruction, a;b - flips the bit a, then jumps to b. This is the most primitive OISC, but it's still useful. It can successfully do math/logic calculations, branching, pointers, and calling functions with the help of its standard library.

<div class="mw-heading mw-heading4"><h4 id="BitBitJump">BitBitJump</h4></div>

A bit copying machine,<a href="#cite_note-mazonka-5">[5]</a> called BitBitJump, copies one bit in memory and passes the execution unconditionally to the address specified by one of the operands of the instruction. This process turns out to be capable of <a href="Universal_computation" class="mw-redirect" title="Universal computation">universal computation</a> (i.e. being able to execute any algorithm and to interpret any other universal machine) because copying bits can conditionally modify the copying address that will be subsequently executed.

<div class="mw-heading mw-heading4"><h4 id="Toga_computer">Toga computer</h4></div>

Another machine, called the <a rel="nofollow" class="external text" href="https://esolangs.org/wiki/TOGA_computer">Toga Computer</a>, inverts a bit and passes the execution conditionally depending on the result of inversion. The unique instruction is TOGA(a,b) which stands for TOGgle a And branch to b if the result of the toggle operation is true.

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<div class="mw-heading mw-heading4"><h4 id="Multi-bit_copying_machine">Multi-bit copying machine</h4></div>

Similar to BitBitJump, a multi-bit copying machine copies several bits at the same time. The problem of <a href="Turing_completeness" title="Turing completeness">computational universality</a> is solved in this case by keeping predefined jump tables in the memory.

<div class="mw-heading mw-heading3"><h3 id="Transport_triggered_architecture">Transport triggered architecture</h3></div>

<a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered architecture</a> (TTA) is a design in which computation is a side effect of data transport. Usually, some memory registers (triggering ports) within common address space perform an assigned operation when the instruction references them. For example, in an OISC using a single memory-to-memory copy instruction, this is done by triggering ports that perform arithmetic and instruction pointer jumps when written to.

<div class="mw-heading mw-heading3"><h3 id="Arithmetic-based_Turing-complete_machines">Arithmetic-based Turing-complete machines</h3></div>

Arithmetic-based Turing-complete machines use an arithmetic operation and a conditional jump. Like the two previous universal computers, this class is also Turing-complete. The instruction operates on integers which may also be addresses in memory.

Currently there are several known OISCs of this class, based on different arithmetic operations:

<ul><li>addition (addleq, add and branch if less than or equal to zero)<a href="#cite_note-esolang-addleq-6">[6]</a></li>

<li>decrement (DJN, Decrement and branch (Jump) if Nonzero)<a href="#cite_note-esolang-djn-7">[7]</a></li>

<li>increment (P1eq, Plus 1 and branch if equal to another value)<a href="#cite_note-esolang-p1eq-8">[8]</a></li>

<li>subtraction (subleq, subtract and branch if less than or equal to zero)<a href="#cite_note-mazonka-subleq-9">[9]</a><a href="#cite_note-esolang-subleq-10">[10]</a></li>

<li>positive subtraction when possible, else branch (Arithmetic machine)<a href="#cite_note-melzak-11">[11]</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Instruction_types">Instruction types</h2></div>

Common choices for the single instruction are:

<ul><li><a href="#Subtract_and_branch_if_less_than_or_equal_to_zero">Subtract and branch if less than or equal to zero</a></li>

<li><a href="#Subtract_and_branch_if_negative">Subtract and branch if negative</a></li>

<li><a href="#Arithmetic_machine">Subtract if positive else branch</a></li>

<li><a href="#Reverse_subtract_and_skip_if_borrow">Reverse subtract and skip if borrow</a></li>

<li><a href="#Transport_triggered_architecture">Move</a> (used as part of a transport triggered architecture)<a href="#cite_note-movfuscator-12">[12]</a></li></ul>

<ul><li><a href="#Subtract_and_branch_if_not_equal_to_zero">Subtract and branch if non zero</a> (SBNZ a, b, c, destination)</li>

<li><a href="#Cryptoleq">Cryptoleq</a> (heterogeneous encrypted and unencrypted computation)</li></ul>

Only one of these instructions is used in a given implementation. Hence, there is no need for an opcode to identify which instruction to execute; the choice of instruction is inherent in the design of the machine, and an OISC is typically named after the instruction it uses (e.g., an SBN OISC,<a href="#cite_note-caamp-2">[2]</a>: 41 the SUBLEQ language,<a href="#cite_note-agut-3">[3]</a>: 4 etc.). Each of the above instructions can be used to construct a Turing-complete OISC.

This article presents only subtraction-based instructions among those that are not transport triggered. However, it is possible to construct Turing complete machines using an instruction based on other arithmetic operations, e.g., addition. For example, one variation known as DLN (Decrement and jump if not zero) has only two operands and uses decrement as the base operation. For more information see Subleq derivative languages <a rel="nofollow" class="external autonumber" href="http://esolangs.org/wiki/Subleq">[1]</a>.

<div class="mw-heading mw-heading3"><h3 id="Subtract_and_branch_if_not_equal_to_zero">Subtract and branch if not equal to zero</h3></div>

The <code>SBNZ a, b, c, d</code> instruction ("subtract and branch if not equal to zero") subtracts the contents at address a from the contents at address b, stores the result at address c, and then, if the result is not 0, transfers control to address d (if the result is equal to zero, execution proceeds to the next instruction in sequence).<a href="#cite_note-agut-3">[3]</a>

<div class="mw-heading mw-heading3"><h3 id="Subtract_and_branch_if_less_than_or_equal_to_zero">Subtract and branch if less than or equal to zero</h3></div>

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</style>subleq instruction ("subtract and branch if less than or equal to zero") subtracts the contents at address a from the contents at address b, stores the result at address b, and then, if the result is not positive, transfers control to address c (if the result is positive, execution proceeds to the next instruction in sequence).<a href="#cite_note-agut-3">[3]</a>: 4–7 <a href="Pseudocode" title="Pseudocode">Pseudocode</a>:

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">subleq a, b, c</code>

Mem[b] = Mem[b] - Mem[a]

if (Mem[b] ≤ 0)

goto c

</pre>

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.

A variant is also possible with two operands and an internal <a href="Accumulator_(computing)" title="Accumulator (computing)">accumulator</a>, where the accumulator is subtracted from the memory location specified by the first operand. The result is stored in both the accumulator and the memory location, and the second operand specifies the branch address:

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">subleq2 a, b</code>

Mem[a] = Mem[a] - ACCUM

ACCUM = Mem[a]

if (Mem[a] ≤ 0)

goto b

</pre>

Although this uses only two (instead of three) operands per instruction, correspondingly more instructions are then needed to effect various logical operations.

<div class="mw-heading mw-heading4"><h4 id="Synthesized_instructions">Synthesized instructions</h4></div>

It is possible to synthesize many types of higher-order instructions using only the subleq instruction.<a href="#cite_note-agut-3">[3]</a>: 9–10

Unconditional branch:

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subleq Z, Z, c

</pre></div></dd></dl>

Addition can be performed by repeated subtraction, with no conditional branching; e.g., the following instructions result in the content at location a being added to the content at location b:

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subleq a, Z

subleq Z, b

subleq Z, Z

</pre></div></dd></dl>

The first instruction subtracts the content at location a from the content at location Z (which is 0) and stores the result (which is the negative of the content at a) in location Z. The second instruction subtracts this result from b, storing in b this difference (which is now the sum of the contents originally at a and b); the third instruction restores the value 0 to Z.

A copy instruction can be implemented similarly; e.g., the following instructions result in the content at location b getting replaced by the content at location a, again assuming the content at location Z is maintained as 0:

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subleq b, b

subleq a, Z

subleq Z, b

subleq Z, Z

</pre></div></dd></dl>

Any desired arithmetic test can be built. For example, a branch-if-zero condition can be assembled from the following instructions:

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subleq b, Z, L1

subleq Z, Z, OUT

L1:

subleq Z, Z

subleq Z, b, c

OUT:

...

</pre></div></dd></dl>

Subleq2 can also be used to synthesize higher-order instructions, although it generally requires more operations for a given task. For example, no fewer than 10 subleq2 instructions are required to flip all the bits in a given byte:

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subleq2 tmp ; tmp = 0 (tmp = temporary register)

subleq2 tmp

subleq2 one ; acc = -1

subleq2 a ; a' = a + 1

subleq2 Z ; Z = - a - 1

subleq2 tmp ; tmp = a + 1

subleq2 a ; a' = 0

subleq2 tmp ; load tmp into acc

subleq2 a ; a' = - a - 1 ( = ~a )

subleq2 Z ; set Z back to 0

</pre></div></dd></dl>

<div class="mw-heading mw-heading4"><h4 id="Emulation">Emulation</h4></div>

The following program (written in <a href="Pseudocode" title="Pseudocode">pseudocode</a>) emulates the execution of a subleq-based OISC:

<div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre> int memory[], program_counter, a, b, c

program_counter = 0

while (program_counter >= 0):

a = memory[program_counter]

b = memory[program_counter+1]

c = memory[program_counter+2]

if (a < 0 or b < 0):

program_counter = -1

else:

memory[b] = memory[b] - memory[a]

if (memory[b] > 0):

program_counter += 3

else:

program_counter = c

</pre></div>

This program assumes that memory[] is indexed by nonnegative integers. Consequently, for a subleq instruction (a, b, c), the program interprets a < 0, b < 0, or an executed branch to c < 0 as a halting condition. Similar interpreters written in a subleq-based language (i.e., <a href="Self-interpreter" class="mw-redirect" title="Self-interpreter">self-interpreters</a>, which may use <a href="Self-modifying_code" title="Self-modifying code">self-modifying code</a> as allowed by the nature of the subleq instruction) can be found in the external links below.

A general purpose <a href="Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a>-capable 64-bit <a href="Operating_system" title="Operating system">operating system</a> called Dawn OS has been implemented in an emulated Subleq machine. The OS contains a <a href="C_language" class="mw-redirect" title="C language">C</a>-like compiler. Some memory areas in the virtual machine are used for peripherals like the keyboard, mouse, hard drives, network card, etc. Basic applications written for it include a media player, painting tool, document reader and scientific calculator.<a href="#cite_note-13">[13]</a>

A 32-bit Subleq computer with a graphic display and a keyboard called Izhora has been constructed by <a href="Yoel_Matveyev" title="Yoel Matveyev">Yoel Matveyev</a> as a large <a href="Cellular_automaton" title="Cellular automaton">cellular automaton</a> pattern.<a href="#cite_note-14">[14]</a><a href="#cite_note-15">[15]</a>

<div class="mw-heading mw-heading4"><h4 id="Compilation">Compilation</h4></div>

There is a <a href="Compiler" title="Compiler">compiler</a> called Higher Subleq written by Oleg Mazonka that compiles a simplified C program into subleq code.<a href="#cite_note-16">[16]</a>

Alternatively there is a self hosting <a href="Forth_(programming_language)" title="Forth (programming language)">Forth</a> implementation written by Richard James Howe that runs on top of a Subleq VM and is capable of interactive programming of the Subleq machine <a href="#cite_note-17">[17]</a>

<div class="mw-heading mw-heading3"><h3 id="Subtract_and_branch_if_negative">Subtract and branch if negative</h3></div>

The subneg instruction ("subtract and branch if negative"), also called SBN, is defined similarly to subleq:<a href="#cite_note-caamp-2">[2]</a>: 41, 51–52

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">subneg a, b, c</code>

Mem[b] = Mem[b] - Mem[a]

if (Mem[b] < 0)

goto c

</pre>

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.

<div class="mw-heading mw-heading4"><h4 id="Synthesized_instructions_2">Synthesized instructions</h4></div>

It is possible to synthesize many types of higher-order instructions using only the subneg instruction. For simplicity, only one synthesized instruction is shown here to illustrate the difference between subleq and subneg.

Unconditional branch:<a href="#cite_note-caamp-2">[2]</a>: 88–89

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre> subneg POS, Z, c

</pre></div></dd></dl>

where Z and POS are locations previously set to contain 0 and a positive integer, respectively;

Unconditional branching is assured only if Z initially contains 0 (or a value less than the integer stored in POS). A follow-up instruction is required to clear Z after the branching, assuming that the content of Z must be maintained as 0.

<div class="mw-heading mw-heading4"><h4 id="subneg4">subneg4</h4></div>

A variant is also possible with four operands – subneg4. The reversal of minuend and subtrahend eases implementation in hardware. The non-destructive result simplifies the synthetic instructions.

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">subneg s, m, r, j</code>

(* subtrahend, minuend, result and jump addresses *)

Mem[r] = Mem[m] - Mem[s]

if (Mem[r] < 0)

goto j

</pre>

<div class="mw-heading mw-heading3"><h3 id="Arithmetic_machine">Arithmetic machine</h3></div>

In an attempt to make Turing machine more intuitive, Z. A. Melzak consider the task of computing with positive numbers. The machine has an infinite abacus, an infinite number of counters (pebbles, tally sticks) initially at a special location S. The machine is able to do one operation:

Take from location X as many counters as there are in location Y and transfer them to location Z and proceed to instruction y.

If this operation is not possible because there is not enough counters in X, then leave the abacus as it is and proceed to instruction n. <a href="#cite_note-18">[18]</a></blockquote>

In order to keep all numbers positive and mimic a human operator computing on a real world abacus, the test is performed before any subtraction. Pseudocode:

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">melzak X, Y, Z, n, y</code>

if (Mem[X] < Mem[Y])

goto n

Mem[X] -= Mem[Y]

Mem[Z] += Mem[Y]

goto y

</pre>

After giving a few programs: multiplication, gcd, computing the n-th prime number, representation in base b of an arbitrary number, sorting in order of magnitude, Melzak shows explicitly how to simulate an arbitrary Turing machine on his arithmetic machine.

<dd><div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>multiply:

melzak P, ONE, S, stop ; Move 1 counter from P to S. If not possible, move to stop.

melzak S, Q, ANS, multiply, multiply ; Move q counters from S to ANS. Move to the first instruction.

stop:

</pre></div></dd></dl>

where the memory location P is p, Q is q, ONE is 1, ANS is initially 0 and at the end pq, and S is a large number.

He mentions that it can easily be shown using the elements of recursive functions that every number calculable on the arithmetic machine is computable. A proof of which was given by Lambek<a href="#cite_note-lambek-19">[19]</a> on an equivalent two instruction machine : X+ (increment X) and X− else T (decrement X if it not empty, else jump to T).

<div class="mw-heading mw-heading3"><h3 id="Reverse_subtract_and_skip_if_borrow">Reverse subtract and skip if borrow</h3></div>

In a reverse subtract and skip if borrow (RSSB) instruction, the <a href="Accumulator_(computing)" title="Accumulator (computing)">accumulator</a> is subtracted from the memory location and the next instruction is skipped if there was a borrow (memory location was smaller than the accumulator). The result is stored in both the accumulator and the memory location. The <a href="Program_counter" title="Program counter">program counter</a> is mapped to memory location 0. The accumulator is mapped to memory location 1.<a href="#cite_note-caamp-2">[2]</a>

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">rssb x</code>

ACCUM = Mem[x] - ACCUM

Mem[x] = ACCUM

if (ACCUM < 0)

goto PC + 2

</pre>

<div class="mw-heading mw-heading4"><h4 id="Example">Example</h4></div>

To set x to the value of y minus z:

<div class="mw-highlight mw-highlight-lang-asm mw-content-ltr" dir="ltr"><pre># First, move z to the destination location x.

RSSB temp # Three instructions required to clear acc, temp [See Note 1]

RSSB temp

RSSB x # Two instructions clear acc, x, since acc is already clear

RSSB x

RSSB y # Load y into acc: no borrow

RSSB temp # Store -y into acc, temp: always borrow and skip

RSSB temp # Skipped

RSSB x # Store y into x, acc

# Second, perform the operation.

RSSB temp

RSSB z # Load z

RSSB x # x = y - z [See Note 2]

</pre></div>

<ul><li>[Note 1] If the value stored at "temp" is initially a negative value and the instruction that executed right before the first "RSSB temp" in this routine borrowed, then four "RSSB temp" instructions will be required for the routine to work.</li>

<li>[Note 2] If the value stored at "z" is initially a negative value then the final "RSSB x" will be skipped and thus the routine will not work.</li></ul>

<div class="mw-heading mw-heading3"><h3 id="Transport_triggered_architecture_2">Transport triggered architecture</h3></div>

<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered architecture</a></div>

A transport triggered architecture uses only the move instruction, hence it was originally called a "move machine". This instruction moves the contents of one memory location to another memory location combining with the current content of the new location:<a href="#cite_note-caamp-2">[2]</a>: 42 <a href="#cite_note-dwj-20">[20]</a>

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">movx a, b</code> (also written a -> b)

OP = GetOperation(Mem[b])

Mem[b] := OP(Mem[a], Mem[b])

</pre>

The operation performed is defined by the destination memory cell. Some cells are specialized in addition, some other in multiplication, etc. So memory cells are not simple store but coupled with an <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) setup to perform only one sort of operation with the current value of the cell. Some of the cells are <a href="Control_flow" title="Control flow">control flow</a> instructions to alter the program execution with jumps, <a href="Addressing_mode#Conditional_execution" title="Addressing mode">conditional execution</a>, <a href="Subroutines" class="mw-redirect" title="Subroutines">subroutines</a>, <a href="If-then-else" class="mw-redirect" title="If-then-else">if-then-else</a>, <a href="For-loop" class="mw-redirect" title="For-loop">for-loop</a>, etc...

A commercial transport triggered architecture microcontroller has been produced called MAXQ, which hides the apparent inconvenience of an OISC by using a "transfer map" that represents all possible destinations for the move instructions.<a href="#cite_note-deh-21">[21]</a>

<div class="mw-heading mw-heading3"><h3 id="Cryptoleq">Cryptoleq</h3></div>

Cryptoleq<a href="#cite_note-crq-22">[22]</a> is a language similar to Subleq. It consists of one <a href="Eponymous" class="mw-redirect" title="Eponymous">eponymous</a> instruction and is capable of performing general-purpose computation on encrypted programs. Cryptoleq works on continuous cells of memory using direct and indirect addressing, and performs two operations O1 and O2 on three values A, B, and C:

<pre>Instruction <code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr">cryptoleq a, b, c</code>

Mem[b] = O1(Mem[a], Mem[b])

if O2(Mem[b]) ≤ 0

IP = c

else

IP = IP + 3

</pre>

where a, b and c are addressed by the instruction pointer, IP, with the value of IP addressing a, IP + 1 point to b and IP + 2 to c.

In Cryptoleq operations O1 and O2 are defined as follows:

<mtr>

<mtd>

<msub>

</mrow>

</msub>

</mtd>

<mtd>

</mtd>

<mtd>

<msup>

</mrow>

</msup>

</mrow>

<msup>

</mrow>

</msup>

</mtd>

</mtr>

</mtable>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle {\begin{array}{lcl}O_{1}(x,y)&=&x^{-1}y\,{\bmod {\,}}N^{2}\end{array}}}</annotation>

</semantics>

</math><img src="./9f36cbed84acc0d9c2ae58ea94e6a9c474d6abd2.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.005ex; width:29.811ex; height:3.176ex;" alt="{\displaystyle {\begin{array}{lcl}O_{1}(x,y)&=&x^{-1}y\,{\bmod {\,}}N^{2}\end{array}}}" loading="lazy"></dd></dl>

<mtr>

<mtd>

<msub>

</mrow>

</msub>

</mtd>

<mtd>

</mtd>

<mtd>

<mrow>

<mfrac>

<mrow>

</mrow>

</mfrac>

</mrow>

</mrow>

</mtd>

</mtr>

</mtable>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle {\begin{array}{lcl}O_{2}(x)&=&\left\lfloor {\frac {x-1}{N}}\right\rfloor \end{array}}}</annotation>

</semantics>

</math><img src="./aaf28b4ad703231e42755f3a5c101fd49b4b23f8.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:19.503ex; height:4.843ex;" alt="{\displaystyle {\begin{array}{lcl}O_{2}(x)&=&\left\lfloor {\frac {x-1}{N}}\right\rfloor \end{array}}}" loading="lazy"></dd></dl>

The main difference with Subleq is that in Subleq, O1(x,y) simply subtracts y from x and O2(x) equals to x. Cryptoleq is also homomorphic to Subleq, modular inversion and multiplication is homomorphic to subtraction and the operation of O2 corresponds the Subleq test if the values were unencrypted. A program written in Subleq can run on a Cryptoleq machine, meaning backwards compatibility. However, Cryptoleq implements fully homomorphic calculations and is capable of multiplications. Multiplication on an encrypted domain is assisted by a unique function G that is assumed to be difficult to reverse engineer and allows re-encryption of a value based on the O2 operation:

<mrow>

<mtr>

<mtd>

<mover>

</mover>

</mrow>

</mtd>

<mtd>

</mrow>

<msub>

</mrow>

</msub>

<mover>

</mover>

</mrow>

</mrow>

</mtd>

</mtr>

<mtr>

<mtd>

<mover>

</mover>

</mrow>

</mtd>

<mtd>

<mtext>otherwise</mtext>

</mrow>

</mtd>

</mtr>

</mtable>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle G(x,y)={\begin{cases}{\tilde {0}},&{\text{if }}O_{2}({\bar {x}}){\text{ }}\leq 0\\{\tilde {y}},&{\text{otherwise}}\end{cases}}}</annotation>

</semantics>

</math><img src="./c5bc79f78c755b55f6d8a5432b370b9b578deb24.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.505ex; width:29.767ex; height:6.176ex;" alt="{\displaystyle G(x,y)={\begin{cases}{\tilde {0}},&{\text{if }}O_{2}({\bar {x}}){\text{ }}\leq 0\\{\tilde {y}},&{\text{otherwise}}\end{cases}}}" loading="lazy"></dd></dl>

where <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\tilde {y}}}">

<mover>

</mover>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle {\tilde {y}}}</annotation>

</semantics>

</math><img src="./9ffa693247786c59ee2c006369c0b00d1e52b0de.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:1.302ex; height:2.509ex;" alt="{\displaystyle {\tilde {y}}}" loading="lazy"> is the re-encrypted value of y and <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\tilde {0}}}">

<mover>

</mover>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle {\tilde {0}}}</annotation>

</semantics>

</math><img src="./2e8a0f60b77336236637abf49da125776834c150.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:1.162ex; height:2.676ex;" alt="{\displaystyle {\tilde {0}}}" loading="lazy"> is encrypted zero. x is the encrypted value of a variable, let it be m, and <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\bar {x}}}">

<mover>

</mover>

</mrow>

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle {\bar {x}}}</annotation>

</semantics>

</math><img src="./466e03e1c9533b4dab1b9949dad393883f385d80.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:1.33ex; height:2.009ex;" alt="{\displaystyle {\bar {x}}}" loading="lazy"> equals ⁠<math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle Nm+1}">

</mstyle>

</mrow>

<annotation encoding="application/x-tex">{\displaystyle Nm+1}</annotation>

</semantics>

</math><img src="./004516bd2d7c12350671799007b8080a2a04b507.svg" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.505ex; width:8.107ex; height:2.343ex;" alt="{\displaystyle Nm+1}" loading="lazy">⁠.

The multiplication algorithm is based on addition and subtraction, uses the function G and does not have conditional jumps nor branches. Cryptoleq encryption is based on <a href="Paillier_cryptosystem" title="Paillier cryptosystem">Paillier cryptosystem</a>.

<ul><li><a href="FRACTRAN" title="FRACTRAN">FRACTRAN</a></li>

<li><a href="Minimal_axioms_for_Boolean_algebra" title="Minimal axioms for Boolean algebra">Minimal axioms for Boolean algebra</a></li>

<li><a href="Register_machine" title="Register machine">Register machine</a></li>

<li><a href="Turing_tarpit" title="Turing tarpit">Turing tarpit</a></li>

<li><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a></li>

<li><a href="Complex_instruction_set_computer" title="Complex instruction set computer">Complex instruction set computer</a></li>

<li><a href="Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">Explicitly parallel instruction computing</a></li>

<li><a href="Minimal_instruction_set_computer" title="Minimal instruction set computer">Minimal instruction set computer</a></li>

<li><a href="Very_long_instruction_word" title="Very long instruction word">Very long instruction word</a></li>

<li><a href="Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">Zero instruction set computer</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFMavaddatParhami,_B.1988" class="citation journal cs1">Mavaddat, F.; Parhami, B. (October 1988). <a rel="nofollow" class="external text" href="http://www.ece.ucsb.edu/~parhami/pubs_folder/parh88-ijeee-ultimate-risc.pdf">"URISC: The Ultimate Reduced Instruction Set Computer"</a> (PDF). International Journal of Electrical Engineering Education. 25 (4). Manchester University Press: 327–334. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1177%2F002072098802500408">10.1177/002072098802500408</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:61797084">61797084</a>. Retrieved 2010-10-04.</cite>

This paper considers "a machine with a single 3-address instruction as the ultimate in RISC design (URISC)". Without giving a name to the instruction, it describes a SBN OISC and its associated assembly language, emphasising that this is a universal (i.e., <a href="Turing-complete" class="mw-redirect" title="Turing-complete">Turing-complete</a>) machine whose simplicity makes it ideal for classroom use.

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Intended for researchers, computer system engineers, computational theorists and students, this book provides an in-depth examination of various OISCs, including SBN and MOVE. It attributes SBN to W. L. van der Poel (1956).

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<li id="cite_note-agut-3">^ <a href="#cite_ref-agut_3-0">a</a> <a href="#cite_ref-agut_3-1">b</a> <a href="#cite_ref-agut_3-2">c</a> <a href="#cite_ref-agut_3-3">d</a> <a href="#cite_ref-agut_3-4">e</a> <a href="#cite_ref-agut_3-5">f</a> <cite id="CITEREFNürnbergWiilHicks2003" class="citation cs2">Nürnberg, Peter J.; Wiil, Uffe K.; Hicks, David L. (September 2003), <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150103161748/http://www.informatik.uni-trier.de/~ley/db/conf/metainformatics/metainformatics2003.html">"A Grand Unified Theory for Structural Computing"</a>, <a rel="nofollow" class="external text" href="http://www.informatik.uni-trier.de/~ley/db/conf/metainformatics/metainformatics2003.html">Metainformatics: International Symposium, MIS 2003</a>, Graz, Austria: <a href="Springer_Science%2BBusiness_Media" title="Springer Science+Business Media">Springer Science+Business Media</a>, pp. 1–16, <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-3-540-22010-7</bdi>, archived from <a rel="nofollow" class="external text" href="https://books.google.com/books?id=uxjigT31ns4C&pg=PA1">the original</a> on 2015-01-03, retrieved 2009-09-07</cite>

This research paper focusses entirely on a SUBLEQ OISC and its associated assembly language, using the name SUBLEQ for "both the instruction and any language based upon it".

</li>

<li id="cite_note-4"><a href="#cite_ref-4">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.bbc.co.uk/news/science-environment-24232896">"First computer made of carbon nanotubes is unveiled"</a>. BBC. 26 September 2013. Retrieved 26 September 2013.</cite>

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<li id="cite_note-mazonka-5">^ <a href="#cite_ref-mazonka_5-0">a</a> <a href="#cite_ref-mazonka_5-1">b</a> Oleg Mazonka, <a rel="nofollow" class="external text" href="http://www.complex-systems.com/pdf/19-3-5.pdf">"Bit Copying: The Ultimate Computational Simplicity"</a>, Complex Systems Journal 2011, Vol 19, N3, pp. 263–285

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<li id="cite_note-esolang-addleq-6"><a href="#cite_ref-esolang-addleq_6-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://esolangs.org/wiki/Addleq">"Addleq"</a>. Esolang Wiki. Retrieved 2017-09-16.</cite>

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<li id="cite_note-esolang-djn-7"><a href="#cite_ref-esolang-djn_7-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://esolangs.org/wiki/DJN_OISC">"DJN OISC"</a>. Esolang Wiki. Retrieved 2017-09-16.</cite>

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<li id="cite_note-esolang-p1eq-8"><a href="#cite_ref-esolang-p1eq_8-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://esolangs.org/wiki/P1eq">"P1eq"</a>. Esolang Wiki. Retrieved 2017-09-16.</cite>

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<li id="cite_note-mazonka-subleq-9"><a href="#cite_ref-mazonka-subleq_9-0">^</a> <cite id="CITEREFMazonka2009" class="citation web cs1">Mazonka, Oleg (October 2009). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170629094925/http://mazonka.com/subleq/index.html">"SUBLEQ"</a>. Archived from <a rel="nofollow" class="external text" href="http://mazonka.com/subleq/index.html">the original</a> on 2017-06-29. Retrieved 2017-09-16.</cite>

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<li id="cite_note-esolang-subleq-10"><a href="#cite_ref-esolang-subleq_10-0">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://esolangs.org/wiki/Subleq">"Subleq"</a>. Esolang Wiki. Retrieved 2017-09-16.</cite>

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<cite id="CITEREFZ._A._Melzak1961" class="citation journal cs1">Z. A. Melzak (1961). <a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-031-9">"An informal arithmetical approach to computability and computation"</a>. <a href="Canadian_Mathematical_Bulletin" title="Canadian Mathematical Bulletin">Canadian Mathematical Bulletin</a>. 4 (3): 279–293. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-031-9">10.4153/CMB-1961-031-9</a>.</cite>

</li>

<li id="cite_note-movfuscator-12"><a href="#cite_ref-movfuscator_12-0">^</a> <cite id="CITEREFxoreaxeaxeax" class="citation web cs1">xoreaxeaxeax. <a rel="nofollow" class="external text" href="https://github.com/xoreaxeaxeax/movfuscator">"movfuscator"</a>. GitHub. Retrieved 2022-11-12.</cite>

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<li id="cite_note-13"><a href="#cite_ref-13">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://users.atw.hu/gerigeri/DawnOS/index.html">"Dawn for SUBLEQ"</a>.</cite>

</li>

<li id="cite_note-14"><a href="#cite_ref-14">^</a> <a rel="nofollow" class="external free" href="https://www.gazetaeao.ru/zanimatelnaya-nauka-vchera-segodnya-zavtra/">https://www.gazetaeao.ru/zanimatelnaya-nauka-vchera-segodnya-zavtra/</a> A Russian article on popular science in <a href="Birobidzhaner_Shtern" title="Birobidzhaner Shtern">Birobidzhaner Shtern</a> with a brief discussion of Yoel Matveyev's Izhora computer

</li>

<li id="cite_note-15"><a href="#cite_ref-15">^</a> <a rel="nofollow" class="external free" href="https://habr.com/ru/post/584596/">https://habr.com/ru/post/584596/</a> A description of the virtual computer Izhora on <a href="Habr" title="Habr">Habr</a> (in Russian)

</li>

<li id="cite_note-16"><a href="#cite_ref-16">^</a> Oleg Mazonka <a rel="nofollow" class="external text" href="https://arxiv.org/abs/1106.2593">A Simple Multi-Processor Computer Based on Subleq</a>

</li>

<li id="cite_note-17"><a href="#cite_ref-17">^</a> Richard James Howe <a rel="nofollow" class="external text" href="https://github.com/howerj/subleq">SUBLEQ eForth</a>

</li>

<li id="cite_note-18"><a href="#cite_ref-18">^</a> <cite id="CITEREFZ._A._Melzak2018" class="citation journal cs1">Z. A. Melzak (2018-11-20) [September 1961]. <a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-032-6">"An informal arithmetical approach to computability and computation"</a>. <a href="Canadian_Mathematical_Bulletin" title="Canadian Mathematical Bulletin">Canadian Mathematical Bulletin</a>. 4 (3): 279–293. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-032-6">10.4153/CMB-1961-032-6</a>.</cite>

</li>

<li id="cite_note-lambek-19"><a href="#cite_ref-lambek_19-0">^</a> <cite id="CITEREFJ._Lambek2018" class="citation journal cs1">J. Lambek (2018-11-20) [September 1961]. <a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-032-6">"How to program an infinite abacus"</a>. <a href="Canadian_Mathematical_Bulletin" title="Canadian Mathematical Bulletin">Canadian Mathematical Bulletin</a>. 4 (3): 295–302. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.4153%2FCMB-1961-032-6">10.4153/CMB-1961-032-6</a>.</cite>

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<li id="cite_note-dwj-20"><a href="#cite_ref-dwj_20-0">^</a> <cite id="CITEREFJones1988" class="citation journal cs1">Jones, Douglas W. (June 1988). <a rel="nofollow" class="external text" href="http://www.cs.uiowa.edu/~jones/arch/risc/">"The Ultimate RISC"</a>. ACM SIGARCH Computer Architecture News. 16 (3). New York: ACM: 48–55. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F48675.48683">10.1145/48675.48683</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:9481528">9481528</a>. Retrieved 2010-10-04.</cite>

"Reduced instruction set computer architectures have attracted considerable interest since 1980. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful."

</li>

<li id="cite_note-deh-21"><a href="#cite_ref-deh_21-0">^</a> <cite id="CITEREFCatsoulis2005" class="citation cs2">Catsoulis, John (2005), Designing embedded hardware (2 ed.), <a href="O'Reilly_Media" title="O'Reilly Media">O'Reilly Media</a>, pp. 327–333, <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-596-00755-3</bdi></cite>

</li>

<li id="cite_note-crq-22"><a href="#cite_ref-crq_22-0">^</a> <cite id="CITEREFMazonkaTsoutsos,_Nektarios_GeorgiosManiatakos,_Michail2016" class="citation cs2">Mazonka, Oleg; Tsoutsos, Nektarios Georgios; Maniatakos, Michail (2016), "Cryptoleq: A Heterogeneous Abstract Machine for Encrypted and Unencrypted Computation", IEEE Transactions on Information Forensics and Security, 11 (9): 2123–2138, <a href="Bibcode_(identifier)" class="mw-redirect" title="Bibcode (identifier)">Bibcode</a>:<a rel="nofollow" class="external text" href="https://ui.adsabs.harvard.edu/abs/2016ITIF...11.2123M">2016ITIF...11.2123M</a>, <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTIFS.2016.2569062">10.1109/TIFS.2016.2569062</a>, <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:261387">261387</a></cite>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="http://esolangs.org/wiki/Subleq">Subleq on the esoteric programming languages wiki</a> – interpreters, compilers, examples and derivative languages</li>

<li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=NmWwRmvjAE8">Reductio ad absurdum</a> on <a href="YouTube_video_(identifier)" class="mw-redirect" title="YouTube video (identifier)">YouTube</a> by Christopher Domas</li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20151121172708/http://www.sccs.swarthmore.edu/users/06/adem/engin/e25/finale/">Laboratory subleq computer</a> – <a href="FPGA" class="mw-redirect" title="FPGA">FPGA</a> implementation using <a href="VHDL" title="VHDL">VHDL</a></li>

<li><a rel="nofollow" class="external text" href="http://catb.org/~esr/retro/#emulators">The Retrocomputing Museum</a> – SBN emulator and sample programs</li>

<li><a rel="nofollow" class="external text" href="http://bitstuff.blogspot.com/2007/02/subtract-and-branch-if-negative.html">Laboratory SBN computer</a> – implemented with <a href="7400_series" class="mw-redirect" title="7400 series">7400 series</a> integrated circuits</li>

<li><a rel="nofollow" class="external text" href="http://esolangs.org/wiki/RSSB">RSSB on the esoteric programming languages wiki</a> – interpreters and examples</li>

<li><a rel="nofollow" class="external text" href="http://www.ddj.com/embedded/221800122?pgno=1">Dr. Dobb's 32-bit OISC implementation</a> – transport triggered architecture (TTA) on an <a href="FPGA" class="mw-redirect" title="FPGA">FPGA</a> using <a href="Verilog" title="Verilog">Verilog</a></li>

<li><a rel="nofollow" class="external text" href="http://www.maxim-ic.com/appnotes.cfm/appnote_number/3222">Introduction to the MAXQ Architecture</a> – includes transfer map diagram</li>

<li><a rel="nofollow" class="external text" href="https://sourceforge.net/projects/oiscemulator">OISC-Emulator</a> – graphical version</li>

<li><a rel="nofollow" class="external text" href="https://github.com/jbangert/trapcc">TrapCC</a> (recent Intel x86 MMUs are actually Turing-complete OISCs.)</li>

<li><a rel="nofollow" class="external text" href="https://github.com/yoelmatveyev/Izhora">Izhora</a> – Yoel Matveyev's Subleq computer built as a cellular automation</li>

<li><a rel="nofollow" class="external text" href="http://cs.drexel.edu/~bls96/oisc/">SBN simulator</a> – simulator and design inspired by <a href="CARDboard_Illustrative_Aid_to_Computation" title="CARDboard Illustrative Aid to Computation">CARDboard Illustrative Aid to Computation</a></li>

<li><a rel="nofollow" class="external text" href="http://laughtonelectronics.com/Arcana/One-bit%20computer/One-bit%20computer.html">One-bit Computing at 60 Hertz</a> – intermediate between a computer and a <a href="State_machine" class="mw-redirect" title="State machine">state machine</a></li>

<li><a rel="nofollow" class="external text" href="https://demin.ws/blog/english/2010/04/06/modelling-a-cpu-with-only-one-operation/">The NOR Machine</a> – info on building a CPU with only one Instruction</li>

<li><a rel="nofollow" class="external text" href="https://github.com/howerj/subleq/">SUBLEQ eFORTH</a> A complete Forth interpreter running on the SUBLEQ OISC.</li>

<li><a rel="nofollow" class="external text" href="https://github.com/momalab/cryptoleq">Cryptoleq</a> – Cryptoleq resources repository</li>

<li><a rel="nofollow" class="external text" href="https://sites.google.com/site/comparchampsite/">CAAMP</a> – Computer Architecture A Minimalist Perspective</li>

<li><a rel="nofollow" class="external text" href="https://deegen1.github.io/sico">SICO</a> – Single Instruction COmputer: a variant of SUBLEQ using unsigned integers</li></ul>

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</style><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox authority-control" aria-label="Navbox391" style="padding:3px"><table class="nowraplinks hlist navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Authority control databases: National </th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><ul><li><a rel="nofollow" class="external text" href="https://d-nb.info/gnd/4761222-8">Germany</a></li></ul></div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Esoteric_programming_languages165" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Esoteric_programming_languages165" style="font-size:114%;margin:0 4em"><a href="Esoteric_programming_language" title="Esoteric programming language">Esoteric programming languages</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Beatnik_(programming_language)" title="Beatnik (programming language)">Beatnik</a></li>

<li><a href="Befunge" title="Befunge">Befunge</a></li>

<li><a href="Brainfuck" title="Brainfuck">Brainfuck</a></li>

<li><a href="FRACTRAN" title="FRACTRAN">FRACTRAN</a></li>

<li><a href="INTERCAL" title="INTERCAL">INTERCAL</a></li>

<li><a href="JSFuck" title="JSFuck">JSFuck</a></li>

<li><a href="LOLCODE" title="LOLCODE">LOLCODE</a></li>

<li><a href="Malbolge" title="Malbolge">Malbolge</a></li>

<li><a href="Shakespeare_Programming_Language" title="Shakespeare Programming Language">Shakespeare Programming Language</a></li>

<li><a href="Unlambda" title="Unlambda">Unlambda</a></li>

<li><a href="Whitespace_(programming_language)" title="Whitespace (programming language)">Whitespace</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div> Category</div></td></tr></tbody></table></div>

</div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-05-25" href="https://en.wikipedia.org/wiki/?title=One-instruction_set_computer&oldid=1292110045">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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